The present invention relates to technology of FPGA, more particularly, to technology of debugging a FPGA design.
FPGA is abbreviation for Field Programmable Gate Array, which is a product further developed on the basis of programmable devices such as Programmable Array Logic (PAL), Generic Array Logic (GAL), Erasable Programmable Logic Device (EPLD), etc. It appears as a semi-customized circuit in field of Application Specific Integrated Circuit (ASIC), it solves the deficiency in customized circuit, while overcomes shortcomings that prior programmable device has limited number of gate circuits.
FPGA employs such a new concept as Logic Cell Array (LCA), which contains three parts therein: Configurable Logic Block (CLB), Input Output Block (IOB) and Interconnect. The basic features of a FPGA are:
1) Using a FPGA to design an ASIC circuit, user can obtain qualified chips without needing to put chip into production.
2) FPGA can act as an intermediate sample chip of other full-customized or semi-customized ASIC circuits.
3) FPGA has abundant flip-flops and I/O pins.
4) FPGA is one of the devices in ASIC circuit that has shortest design period, lowest development cost and lowest risk.
5) FPGA employs a high speed Complementary High-performance Metal Oxide Semiconductor (CHMOS) process, which has low power consumption, and is compatible with Complementary Metal Oxide Semiconductor (CMOS), transistor-transistor logic (TTL) level.
It can be said that FPGA chip is one of the best choices for small batch system to improve system integrity and reliability.
After more than ten years' development, a number of companies have developed various programmable logic devices. Among them are Xilinx's FPGA device series and Altera's CPLD device series, which are developed early and occupy a relative large portion of PLD market.
The working state of a FPGA is set by the program stored in on-chip Random Access Memory (RAM), therefore, the on-chip RAM needs to be programmed during working. User can employ different programming manners according to different configuration modes.
When powering on, the FPGA chip reads data in Erasable Programmable Read Only Memory (EPROM) into on-chip programmable RAM, after configuration, the FPGA enters working state. When powering off, the FPGA restores to a blank chip and its internal logic relationship disappears. Thus, FPGA can be used repeatedly. FPGA's programming does not need special FPGA programmer, and only use generic EPROM, PROM (Programmable Read Only Memory) programmer. When there is a need to modify the FPGA function, what is needed is to replace the EPROM. Thus, a same piece of FPGA with different programming data can yield different circuit functions. Therefore, the usage of FPGA is very flexible.
A FPGA has a number of configuration modes: parallel master mode is one piece of FPGA plus one piece of EPROM; master slave mode can support using one piece of PROM to program multiple pieces of FPGA; serial mode can use serial PROM to program FPGA; peripheral mode can use FPGA as peripheral device of a microprocessor and the FPGA is programmed by the microprocessor.
FPGA's designer generally will test and debug the FPGA before manufacturing the FPGA in large scale for commercial purposes. The designer hopes to detect signals coming into/from a FPGA, so that the designer can identify and correct any design problems (for example, programming errors) related to the FPGA.
However, with the complexity of FPGA design increases, FPGA's debugging becomes a big challenge to digital system designers. Currently used debugging manner includes using a logic analyzer or JTAG (Joint Test Action Group) based software debugger to trace behavior and signals in the FPGA.
A method that uses logic analyzer generally needs to connect the logic analyzer to the FPGA. The designer then uses the logic analyzer to capture samples of these signals. However, this method needs to route FPGA's internal nodes to some physical I/O pins, so that the logic analyzer's probe can be connected to these physical pins to perform detection. While it is a very useful method, it has significant drawbacks:
I/O pins are very expensive resources in FPGA, and only a few numbers of I/O pins are available for testing and debugging;
it has problem of signal intensity and time delay;
it requires additional layer and is difficult to design, thereby increases PCB (Printed Circuit Board) cost;
this debugging method is unilateral, it can only capture FPGA's internal signal through the logic analyzer, and could not input designer's desired test or stimulation signal.
A method that uses JTAG based software debugger generally needs to use internal logic resources to build trigger logic and store sample data in on-chip SPAM, then send the sample data to PC (Personal Computer) via JTAG cable. Although this method is a low cost solution for FPGA debugging, it has significant drawbacks:
it uses FPGA internal SRAM as sample buffer, which may affects logic design;
sample depth is restricted by capacity of SRAM;
the response time is long and could not capture continuous data flow;
the trigger function is restricted.